1. Technical Field
The present invention relates in its more general aspect to a memory cells device, in particular of the NOR Flash type.
More specifically, the invention relates to a method for programming a memory cell, in particular, of the NOR Flash type.
The invention also relates to a suitable circuit to be associated to the basic circuit of the NOR Flash memory cells device in order to implement such a programming method.
2. Description of the Related Art
As it is well known, the reduction of the programming time can be considered one of top requests from Flash memories customers to their suppliers.
The use of the currently available programming method makes more and more difficult to guarantee both a good matching of the time specifications for programming and small distribution width in order to allow the allocation of all bits of a generic multilevel NOR Flash cell. For this reason the introduction of a statistical correction (ECC, or Error Correction Code) or an increasing of the gap among the reference levels has been necessary so far when programming multilevel memory cells.
It is worth reminding that the currently available NOR Flash cells are usually programmed in two phases:                a programming phase, by means of a sequence of programming voltage pulses, or program pulses and        a verify reading phase, by means of a sequence of verify reading voltage pulses, or verify pulses.        
In particular, during the programming phase, the sequence of program pulses is firstly applied to the cell gate terminal. The pulse amplitude grows at each subsequent program step, according to a time/voltage ramp. Always during the programming phase, the drain voltage value is set to a first fixed voltage value Vd_prog (for instance, equal to 4.2 V).
During the verify reading phase, the voltage value of the drain terminal is set to a second voltage value Vd_ref (for instance, equal to 0.7 V), lower than the first voltage value Vd_prog used for the programming phase (usually set to 4.2V), and a verify reading of the cell threshold voltage value is performed between two consecutive (or chained) program pulses, by applying to the cell gate terminal a verify pulse belonging to the sequence of verify reading voltage pulses, whose amplitude is held constant in any case.
If the so measured cell threshold voltage value turns out to be below a desired program reference level, a further program pulse of the programming voltage pulses sequence is applied to the cell gate terminal. On the contrary, in case the so measured threshold voltage value is above the desired program reference level, the programming phase is concluded and the cell is considered to have been programmed.
The overall programming time can be considered as the sum of the time duration of all pulses, both program and verify pulses, needed to set the threshold voltage value of a cell to the desired program reference level, along with the time requested by the algorithms and the analog circuit, which is connected to the cell for its programming, to switch from a program pulse to a verify pulse, and vice versa.
The main problem related to the previously known programming method is that the request of small distribution width of the cell threshold voltages corresponding to the different programming levels is an issue opposing to the reduction of the programming time, since, in order to have smaller distributions width, the frequency of the verify pulses has to be increased during programming or soft programming phases, ultimately increasing the overall programming time of the cell.
In a multilevel NOR Flash cell the above problem becomes even more critical with respect to a single level cell, because in the first case a higher number of programmed distributions must be contained in a voltage range which becomes smaller and smaller due to the continuous dimension scaling down of silicon integration technologies of the Flash NOR memories. Such a voltage range spans between a minimum voltage level, equal to a voltage value required to have no leakage in the array of NOR Flash cells, and a maximum voltage, equal to a voltage value required to limit the number of failed memory devices for retention issues.
The known programming method for NOR Flash cells used so far, and described here above, does not allow finding an appropriate trade-off between the demand of improving the programming precision, i.e. achieving a smaller distributions width, and the demand of reducing the programming time.